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| clocks { #address-cells = <1>; #size-cells = <1>; ranges;
dummy: dummy { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; };
osc24M: osc24M@01c20050 { #clock-cells = <0>; compatible = "allwinner,sun4i-osc-clk"; reg = <0x01c20050 0x4>; clock-frequency = <24000000>; };
osc32k: osc32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; };
pll1: pll1@01c20000 { #clock-cells = <0>; compatible = "allwinner,sun4i-pll1-clk"; reg = <0x01c20000 0x4>; clocks = <&osc24M>; };
cpu: cpu@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-cpu-clk"; reg = <0x01c20054 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; };
axi: axi@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-axi-clk"; reg = <0x01c20054 0x4>; clocks = <&cpu>; };
axi_gates: axi_gates@01c2005c { #clock-cells = <1>; compatible = "allwinner,sun4i-axi-gates-clk"; reg = <0x01c2005c 0x4>; clocks = <&axi>; clock-output-names = "axi_dram"; };
ahb: ahb@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-ahb-clk"; reg = <0x01c20054 0x4>; clocks = <&axi>; };
ahb_gates: ahb_gates@01c20060 { #clock-cells = <1>; compatible = "allwinner,sun4i-ahb-gates-clk"; reg = <0x01c20060 0x8>; clocks = <&ahb>; clock-output-names = "ahb_usb0", "ahb_ehci0", "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", "ahb_de_fe1", "ahb_mp", "ahb_mali400"; };
apb0: apb0@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb0-clk"; reg = <0x01c20054 0x4>; clocks = <&ahb>; };
apb0_gates: apb0_gates@01c20068 { #clock-cells = <1>; compatible = "allwinner,sun4i-apb0-gates-clk"; reg = <0x01c20068 0x4>; clocks = <&apb0>; clock-output-names = "apb0_codec", "apb0_spdif", "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", "apb0_ir1", "apb0_keypad"; };
/* dummy is pll62 */ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; clocks = <&osc24M>, <&dummy>, <&osc32k>; };
apb1: apb1@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&apb1_mux>; };
apb1_gates: apb1_gates@01c2006c { #clock-cells = <1>; compatible = "allwinner,sun4i-apb1-gates-clk"; reg = <0x01c2006c 0x4>; clocks = <&apb1>; clock-output-names = "apb1_i2c0", "apb1_i2c1", "apb1_i2c2", "apb1_can", "apb1_scr", "apb1_ps20", "apb1_ps21", "apb1_uart0", "apb1_uart1", "apb1_uart2", "apb1_uart3", "apb1_uart4", "apb1_uart5", "apb1_uart6", "apb1_uart7"; }; };
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